ASICs and FPGAs — market trends

Being involved in FPGA and reconfigurable device research means that I’ve sat in the audience of a lot of talks that have touted the fact that ASIC “starts” are declining and FPGA starts are just blowin’ up. What is an ASIC design start? From Synopsis, it’s a “single design, designed to one system-level application, for one customer”.

Of course, the data doesn’t always get cited correctly, which really irked me, so I started digging around. The source of these numbers is actually a set of Gartner/Dataquest market research reports that, unfortunately, cost some real dollars to obtain. So, can we actually paste together the real and forecasted numbers for ASIC and FPGA starts through everyone’s paraphrasing of the Gartner research? Let’s try.

Electronic Design reports back in September of 2003 that Gartner number of predicted ASIC starts for 2003 was 4000. No mention of FPGA starts. But strangely, Electronics Design Chain Magazine quotes from an IC Insights report saying there were 5,200 standard-cell ASIC starts in 1997, and 1,400 in 2003. Hrmph. But now, a site called Electronicstalk quotes from another Gartner report (which one are we talking about people? Cite!) which says that structured ASICs (more on that in a bit) will number 1,000 by 2007, and be 25% of all ASIC design starts. That’s 4,000 total ASIC design starts predicted in 2007 in a Gartner report sometime before September 14, 2004. Given lots of reports are calling for zero or negative growth in the number of ASIC design starts (not structured ASICs), 4,000 by 2007 sounds about right. Now let’s find an FPGA reference.

June 13, 2005, EETimes reports that Gartner says FPGA starts in 2005 are projected at 80,000, with growth to 110,000 by 2010, dwarfing ASIC starts. Gartner also says that “platform” or “structured” ASICs are going to be big in the coming years. More on that in a bit. Important to note here that ASIC designs make a ton more money than FPGA designs. Let’s see about that.

March 22, 2004, Electronic News paraphrases that Gartner predicted 2004 ASIC revenue at $18B, while FPGA revenue $3.1B. Big growth occurred in Asia, particularly in Taiwan and China. Bottom line in that report — there is room enough for both FPGAs and ASICs in the world. Driving this market, again, structured ASICs are cited. So let’s go there.

What the heck is a structured ASIC? Is it starched and neatly folded? Nope. It’s a neat hybrid of prefabricated pieces and custom routing. Everyone has their own definition, but here’s the basic idea. The cost of fabricating an ASIC is in the building of the masks — one per layer. With some processes approaching 10 layers of metal, and all the bits that actually compose the transistor-making layers, that’s a lot of mask sets. If we want to be able to optically focus down to 65nm, those masks are not going to be cheap. Try millions of dollars or more. So, what do you do? Take the basic reconfigurable logic block elements that make up a typical FPGA — datapath bits, like lookup tables, adders, multipliers, etc., and put them down in prefabricated layers. These are tested parts, and they just work. They remain reprogrammable through SRAM bit configuration, say, so we can implement generic logic. Now, instead of routing them with SRAM-controlled switch and connection blocks, which add significant amounts of delay (and consume significant amounts of chip real-estate), we just wire it together with a fixed routing structure that we define in one or more real metal layers, vias and all.

What’s that get us? Well, first off, we only need to make one or two masks for the routing layers so the cost is way down per unit in volume. We also get faster interconnects and perhaps better area utilization — this may give us faster overall designs. Reliability may also be higher because we are using known-good basic building blocks for our logic. We also get the likely ability to prototype using regular FPGAs since the underlying structure is very much like those programmable devices (and you can even buy them straight from Altera). With that you get easy debugging and near instant gratification. When you want to roll out 2 million parts, instead of the $22 FPGA, you use the much cheaper cheap-ASIC fabrication to get your costs down in volume.

What do we lose? Well, we might need to learn a whole different tool flow. Cadence has a flow that can target various structured-ASIC vendors. Other vendors have their own tool flows. There is also a density issue. You aren’t going to beat even standard-cell ASIC flows with this, as the logic density is way lower. But, perhaps the payoffs are big if you need volume and time to market.

So what does the esteemed Gartner say about structured ASICs? Well, November 18, 2003 saw a report entitled, “Platform ASICs Jump-Start Market”… with “platform ASICs” meaning the same thing as structured ASICs.

So, who makes structured ASICs? Fujitsu, LSI Logic, Altera, eASIC, Lightspeed, just to name a few. For more information, check out this good report on alternatives to ASICs.

So, how far did we come on finding out about the Gartner/Dataquest report? I think we just end up repeating the mantra… ASIC starts are declining, hitting maybe 4,000 somewhere between 2003 and 2007. FPGA starts are increasing, hitting somewhere between 8,000 and 110,000 by 2007. The ASIC world makes more cash, but don’t count out the reprogrammable industry. Gah. Cite your sources people!

Some Gartner reports, if you have the cash. They are not linked, but referenced by ID number, as Gartner has a stupid web system:

• (G00129557) 9 August 2005, EDA Vendors Should Keep Serving Both ASIC and FPGA Designers
• (G00136594) 12 December 2005, Semiconductor Industry Survivors Will Embrace Six Trends
• (SEMC-WW-EX-0333) 19 March 2004, Technology Road Map to Future ASIC and FPGA Designs (Executive Summary)
• (G00126145) 7 February 2004, Market Trends: ASIC and FPGA, Worldwide, 2002-2008, 1Q05 Update (Executive Summary)